Sun Feb 3 13:45:16 CET 2013


Talk by Connor Abbot[1] about the Mali 200/400 pixel processor (PP)
and geometry processor (GP).  IIRC the PP is a fairly general purpose,
deeply pipelined core, while the GP is a VLIW with a "feedback FIFO"

The part last struck me as interesting: reading and writing ALU
results from/to registers requires multi-port registers, which is
expensive in silicon.  A simple hardware trick is to feed back the
output of the ALU to make it available on the next cycle in an array
of FIFOs, which are cheaper than full-fledged readable/writable

[1] https://fosdem.org/2013/schedule/event/maliisa/