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Sat Feb 5 12:16:23 EST 2011

SPI basics

The SPI bus is a point-to-point connection with one master and one
slave.  The master generates the clock. There are 4 signal lines:

    MISO: master input slave output
    MOSI: master output slave input
    SCK:  master clock
    SS:   slave select (CS: chip select)

The MISO/MOSI naming connects pins with same names.  An alternative
naming scheme:

    SDO: serial data out
    SDI: serial data in

names pins according to data direction.  This requires SDO<->SDI
connections.  Some remarks:

* Implicit in what I read, but it seems that master/slave choices are
  a property of the circuit design, i.e. they won't change during
  operation.  As a consequence, all signals are uni-directional.  It
  also seems plausible that a "dumb" device like a sensor or storage
  device will not be master.

* When a slave is not enabled (SS high) the MISO (a.k.a. SDO) pin is
  in high-Z configuration.  Does this require a pullup/down on the bus
  to avoid noise?  I guess not as the input can be ignored by the
  master during the time no slave is active.

* Communication is full duplex when the master drives the clock.
  There are 4 clock modes: 2 clock polarities times 2 read/write edge
  configurations.

* Data seems to be MSB first (from SST25 and PIC18 data sheet).
  However SPI transfers bits, not bytes or words so it seems to be up
  to the device.

* PIC18F2620 can use TMR2 / 2 or FOSC / 4,16,64 as master clock freq.
  ( While the other times have 2^n subdivisions, TMR2 has a period
  register so can be quite flexible. )

* In both the PIC18 and AT91SAM7 data sheets the master mode sends 8
  bits at a time, sending MSB first.  ( The PIC18 has one dead cycle
  after the 8th bit is sent out with the last asserted data bit still
  present.  I've seen this using the SPI out as a video shift
  register.  Since this is also a dead clock cycle, it doesn't matter
  for slaves. )


[1] http://en.wikipedia.org/wiki/SPI_bus




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