Fri Oct 2 13:25:36 CEST 2009
MyHDL by Jan Decaluwe. An LtU thread here. An EE times
A python-based HDL & modeling tool based on generators and decorators.
In MyHDL, classic functions are used to model hardware modules. In
particular, the parameter list is used to define the interface.
Nested functions, generators and decorators should map cleanly to
lambda abstractions, lightweight threads and mixins.
I like the fact that generators are used instead of classes. This
seems to be quite natural, as most OO-based dataflow code is centered
around a 'process' method. Python generators are not generators in
the traditional sense (they wrap just an instruction pointer, not a
call stack), so a state-machine model is sufficient to implement
them. This principle should be mappable to C code in a straight way
generation of fast simulators.
One of the more interesting aspects of MyHDL is the way in which
conversion to Verilog is done:
The conversion does not start from source files, but from an
instantiated design that has been elaborated by the Python
interpreter. The converter uses the Python profiler to track the
interpreter's operation and to infer the design structure and name
spaces. It then selectively compiles pieces of source code for
additional analysis and for conversion. This is done using the
Python compiler package.