Sat Aug 3 16:45:00 EDT 2013


Looked at MyHDL and found out that my initial understanding was wrong:
it does not use generators to implement state machines (FSMs).

It uses generators to implement events, i.e. signal change wait
points.  Values returned by a generator are used by the MyHDL
scheduler to wake up simulations.

The reason has probably to do with synthesizability.  I'm not sure
exactly how that works in MyHDL, but it seems that an *implicit* FSM
in the form of a generator is too opaque to recover state.  This is an
essential part of the abstract-syntax-oriented approach I'm proposing:
access to syntax is essential because a syntacting transformation is
necessary to map yield/wait syntax to state machines.