Fri Aug 2 11:36:00 EDT 2013
Writing a deeply embedded program as a collection of state machines
removes the need for an RTOS. This can be good, because an rtos by
itself is a big requirement, and threads are usually not very
efficient. Especially so if a proper factorization of a problem would
contain many different threads.
So, I've been thinking about writing a (simple) racket system that
combines ideas from
- Antti's Bream
- Tom Hawkins' Atom
Basically, tail-recursive Scheme code (without any real recursion or
re-entry) is a relatively high-level way for writing state machines,
as it solves the variable binding problem: Scheme's lexical scope
avoids a global state structure with lingering "don't care" variables
as would be the case in an explicit C implementation.
Such a scheme program can be turned "inside-out" to yield a C
implementation with all blocking points turned into exits + state
entry (condition==true is mapped to state change).
An optimized implementation could use register re-use.
So simple, no-frills approach could work well.
( What I'm describing here is probably 90% of what is in existing good
C compiler for a small microcontrollers. )
So what's the concrete problem I want to solve?
Build a translator from shallow (non-properrecursive) tail-recursive
blocking Scheme code to non-blocking state machines with a condition
abstraction. Write it the way a microcontroller works:
- allow for polling operation: do state transition when READY flag
- allow for interrupt: avoid polling, just run the update when an
interrupt occurs, notifying a certain flag is set.
Looking at VHDL's sensitivity lists: these seem to be there only for
simulation, i.e. to update the state of a process whenever an input
changes. Synthesized logic will do whatever its circuit does.
Essentially this is the bridge between a physical system (the circuit)
and a simplified model: an event-driven digital system.