Wed Dec 12 12:55:57 EST 2012


Source (23.6.3)
0: FIQ pin 
1: SIQ system peripheral interrupt lines (system timer, RTC, PMC, MC, ...)
2-31: PID2-PID31: embedded user peripheral / external interrupt lines

What's the difference between system/user peripheral?  E.g. PIO is a
user peripheral. The peripheral identification defined at the product
level corresponds to the interrupt source number.

For a peripheral table, see 10.2

Registers: (* = E/D or S/C)
AIC_SMR   source mode register
AIC_I*CR  interrupt enable/disable command register
AIC_I*CR  interrupt set/clear command register
AIC_IPR   interrupt pending
AIC_IVR   interrupt vector (read signals entry of ISR)
AIC_IMR   interrupt mask
AIC_ISR   current interrupt (p158)
          fast forcing
AIC_EOICR end of interrupt command register (to signal exit of ISR)
AIC_SVRn  source vector register n:1-31 (corresponds to AIC_IVR read)

The basic idea behind the AIC is to extend the ARM's simple
single-interrupt model to a multi-priority interrupt model by running
bulk of the ISR routines with arm IRQ enabled.

AIC enables fast vectored dispatch to allow for lower interrupt
latencies.  For such routines, care needs to be taken to complete the
AIC entry/exit in each routine.  The AIC uses a stack internally to
keep track of the current interrupt being served.  Entry/exit are
marked by r/w of AIC_IVR and AIC_EOICR.

[1] http://www.atmel.com/Images/doc6120.pdf