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Thu Jun 23 13:37:11 CEST 2011

OpenOCD: reset halt vs. reset init

If the target under debug gets switched off while a debug setting is
running, issuing a "reset halt" isn't enough.  I verfied this and I
got faulty JTAG communication, but "poll" did work.  After "reset
init" things are back to normal.

(gdb) mon slow_reset halt
100 kHz
srst pulls trst - can not reset into halted mode. Issuing halt after reset.
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x200000d3 pc: 0x00005bb8
1000 kHz
(gdb) mon poll
background polling: on
TAP: at91sam7s256.cpu (enabled)
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x200000d3 pc: 0x00005bb8
(gdb) vstepi
Bad value '00000001' captured during DR or IR scan:
 check_value: 0x00000009
 check_mask: 0x00000009
JTAG error while reading cpsr
Bad value '00000001' captured during DR or IR scan:
 check_value: 0x00000009
 check_mask: 0x00000009
JTAG error while reading cpsr
Couldn't calculate PC of next instruction, current opcode was 0x00000000
0x00005bb8 in ?? ()
   0x5bb0:      andeq   r0, r0, r0
   0x5bb4:      andeq   r0, r0, r0
=> 0x5bb8:      andeq   r0, r0, r0
   0x5bbc:      andeq   r0, r0, r0
   0x5bc0:      andeq   r0, r0, r0
   0x5bc4:      andeq   r0, r0, r0
   0x5bc8:      andeq   r0, r0, r0
   0x5bcc:      andeq   r0, r0, r0
   0x5bd0:      andeq   r0, r0, r0
   0x5bd4:      andeq   r0, r0, r0



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