Sat May 28 12:14:09 CEST 2011
OpenOCD on the AT91
It's slow and I don't know why. Setting debug loglevel gives this as
the main programming loop:
Debug: 15414 145857 target.c:1652 target_write_u32(): address: 0xffffff64, value: 0x5a03d801
Debug: 15415 145857 embeddedice.c:502 embeddedice_write_reg(): 0: 0x00000004
Debug: 15416 145857 embeddedice.c:502 embeddedice_write_reg(): 0: 0x00000005
Debug: 15417 145873 at91sam7.c:353 at91sam7_flash_command(): Flash command: 0x5a03d801, flash bank: 1, page number: 984
Debug: 15418 145874 arm7_9_common.c:2270 arm7_9_read_memory(): address: 0xffffff68, size: 0x00000004, count: 0x00000001
Debug: 15420 145889 target.c:1575 target_read_u32(): address: 0xffffff68, value: 0x00000401
Debug: 15421 145889 at91sam7.c:328 at91sam7_wait_status_busy(): status: 0x401
Debug: 15422 145889 at91sam7.c:1102 at91sam7_write(): Write flash bank:0 page number:984
Debug: 15423 145889 embeddedice.c:502 embeddedice_write_reg(): 0: 0x00000004
Debug: 15424 145889 embeddedice.c:502 embeddedice_write_reg(): 0: 0x00000005
So what we see here is that the flash command 0x5a03d801 goes to
register 0xffffff64. Looking at the data sheet this is a block of 256
registers called MC (memory controller) at 0xffffff00, which is
documented in section 18 in the AT91SAM7X datasheet. At offset 60 and
70 in this window are two EFCs : embedded Flash Controllers which are
documented in section 19.
0x64 : MC_FCR : Memory Controller Flash Command Register
5A 0 3D8 0 1
key page command
= WP (write page)
The key is the write-protection key, always 0x5A
0x68 : MC_FSR : Memory Controller Flash Status Register
bit 0 is the ready bit.
-> find out if this causes the delay
No it doesn't : that bit is 1 when it's read.
Ok, I tried again on the host and I get 7kByte/sec, but it doesn't
Why is this so buggy? I had similar problems a couple of months ago.
Is it just that I miss some console messages, or is it electrical?
I think it's worth investing some time to see how this actually works,
so I can understand the error messages.