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Tue May 15 16:03:10 EDT 2018

Next: configure PRU pins

This is a pinmux thing.  Where is that configured?
dtc is now on the target, so have it dump config.

EDIT:

# cat /usr/bin/dts.sh
#!/bin/sh
exec dtc -I fs -O dts /sys/firmware/devicetree/base

dts.sh |grep P9

Looking at that file doesn't help me much, but it might be good to
start from a concrete goal: I want to put 10MHz on PRU1 GPO pin 0.


Search for this backwards:

R1  P8_45  pr1_pru1_pru_r30_0   GPIO2_6

http://ofitselfso.com/BeagleNotes/UsingDeviceTreesToConfigurePRUIOPins.php
- build and execute DT overlay
- mount -t debugfs none /sys/kernel/debug
- /sys/kernel/debug/pinctrl/44e10800.pinmux/pins

      Bit Number       8 7 6 5 4 3 2 1 0 
                           c r s p m m m     
m = 3 mode bits [0-7]     
p = 0 pullups/pulldowns enabled, 1 pullups/pulldowns disabled
s = 0 pulldown selected, 1 pullup selected     
r = 0 pin is output, 1 pin is input
c = 0 fast slew control, 1 = slow slew control

"is the PinMux pin at offset 0x838 in use by anything else"?

/sys/kernel/debug/pinctrl/44e10800.pinmux/pinmux-pins


P8_16 Mode6

/*
 * This is a template-generated file from BoneScript
 */

/dts-v1/;
/plugin/;

/{
    compatible = "ti,beaglebone", "ti,beaglebone-black";
    part_number = "BS_PINMODE_P8_16_0x26";

    exclusive-use =
        "P8.16",
        "pr1_pru0_pru_r31_14";

    fragment@0 {
        target = <&am33xx_pinmux>;
        __overlay__ {
            bs_pinmode_P8_16_0x26: pinmux_bs_pinmode_P8_16_0x26 {
                pinctrl-single,pins = <0x038 0x26>;
            };
        };
    };

    fragment@1 {
        target = <&ocp>;
        __overlay__ {
            bs_pinmode_P8_16_0x26_pinmux {
                compatible = "bone-pinmux-helper";
                status = "okay";
                pinctrl-names = "default";
                pinctrl-0 = <&bs_pinmode_P8_16_0x26>;
            };
        };
    };
};




So questions.
- Why are there two things instead of one?
- What the fuck does this all mean?


Aha. There are two things, because the top one creates a node inside
the am33xx_pinmux node, and the bottom one references it.

It seems the parent node (ocp) is rather arbitrary.



So how to do this:
- look up the pin mode in 
/sys/kernel/debug/pinctrl/44e10800.pinmux/pins




In reference manual, pinmux is part of
44C00000 L4_WKUP 
44E10000 Control Module
44E10800 pin mux

Pin mux documentation is in 9.3.1.50 conf_<module>_<pin> register,
and Table 9-10, Control Module Registers Table/

See /sys/kernel/debug/pinctrl/44e10800.pinmux/pins
This relates pin number, pin control address and control value.

Now, how to map Beaglebone P8,P9 pins to mux pin number?

I still want this one:

R1  P8_45  pr1_pru1_pru_r30_0   GPIO2_6

So let's grep in linux/arch/arm/boot/dts/*bone*

Found something here: am335x-bone-common-universal.dtsi

        P8_45_pinmux {
                compatible = "bone-pinmux-helper";
                status = "okay";
                pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin","pwm", "hdmi";
                pinctrl-0 = <&P8_45_default_pin>;
                pinctrl-1 = <&P8_45_gpio_pin>;
                pinctrl-2 = <&P8_45_gpio_pu_pin>;
                pinctrl-3 = <&P8_45_gpio_pd_pin>;
                pinctrl-4 = <&P8_45_pruout_pin>;
                pinctrl-5 = <&P8_45_pruin_pin>;
                pinctrl-6 = <&P8_45_pwm_pin>;
                pinctrl-7 = <&P8_45_hdmi_pin>;
        };

The individual pin configurations are in am335x-bone-common-universal-pins.dtsi

        /* P8_45 (ZCZ ball R1 ) hdmi    */
        P8_45_default_pin: pinmux_P8_45_default_pin {
                pinctrl-single,pins = <0x0a0  0x27>; };     /* Mode 7, Pull-Down, RxActive */
        P8_45_gpio_pin: pinmux_P8_45_gpio_pin {
                pinctrl-single,pins = <0x0a0  0x2F>; };     /* Mode 7, RxActive */
        P8_45_gpio_pu_pin: pinmux_P8_45_gpio_pu_pin {
                pinctrl-single,pins = <0x0a0  0x37>; };     /* Mode 7, Pull-Up, RxActive */
        P8_45_gpio_pd_pin: pinmux_P8_45_gpio_pd_pin {
                pinctrl-single,pins = <0x0a0  0x27>; };     /* Mode 7, Pull-Down, RxActive */
        P8_45_pruout_pin: pinmux_P8_45_pruout_pin {
                pinctrl-single,pins = <0x0a0  0x05>; };     /* Mode 5, Pull-Down*/
        P8_45_pruin_pin: pinmux_P8_45_pruin_pin {
                pinctrl-single,pins = <0x0a0  0x26>; };     /* Mode 6, Pull-Down, RxActive */
        P8_45_pwm_pin: pinmux_P8_45_pwm_pin {
                pinctrl-single,pins = <0x0a0  0x03>; };     /* Mode 3, Pull-Down*/
        P8_45_hdmi_pin: pinmux_P8_45_hdmi_pin {
                pinctrl-single,pins = <0x0a0  0x08>; };     /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */



Questions:
- what is "bone-pinmux-helper"?
- what does "compatible" mean?

What I get from this is that pinmux allows to switch between pincontrols.

Also, I probably need to disable HDMI.

HDMI is 40-59 44e108a0-44e108ec



# cat pinmux-pins |grep hdmi
pin 40 (PIN40): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 41 (PIN41): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 42 (PIN42): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 43 (PIN43): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 44 (PIN44): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 45 (PIN45): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 46 (PIN46): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 47 (PIN47): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 48 (PIN48): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 49 (PIN49): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 50 (PIN50): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 51 (PIN51): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 52 (PIN52): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 53 (PIN53): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 54 (PIN54): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 55 (PIN55): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 56 (PIN56): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 57 (PIN57): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 58 (PIN58): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 59 (PIN59): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins
pin 108 (PIN108): 0-0070 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins




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