Thu Feb 1 14:54:05 EST 2018
PRU SRAM->DRAM path
PRU1 is the sampler: R31 -> R21-R28, then across broadside
XOUT 10, &R21, 36
LDI R31, PRU1_PRU0_INTERRUPT + 16 ; jab PRU0
PRU0 moves data from register file out to RAM?
; Wait for and clear the buffer ready signal from PRU1
WBS R31, 30
SBCO &R0, C0, 0x24, 4
XIN 10, &R21, 36 ; Get the logic data from PRU1
SBBO &R21, R18, 0, 32 ; Write buffer
; Signal ARM that one buffer is now ready
LDI R31, 32 | (SYSEV_PRU0_TO_ARM_A - 16)
- broadside connect with XOUT,XIN ?
PRU0/1 Scratch Pad
Scratch pad (SPAD) memory and broadside direct connect, transfer in
one clock cycle between PRU0,SPAD, then again SPAD,PRU1. There are 3
- SBCO, SBBO?
Store Byte Burst with Constant Table Offset (SBCO)
Store Byte Burst (SBBO)
So what memory does this go into? Passed into the run() routine.
It's passed in through capture_context which is set at 0x0000
So it appears that:
- ARM can access this memory
- We can write in to ARM memory
pruss_request_mem_region(bldev->pruss, PRUSS_MEM_DRAM0, &bldev->pru0sram);
Phytec alsho has a board.. Here's some source:
For code, it seems simplest to start the project as a modification of
the beagle logic PRU firmware and Linux driver.